Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices), radiation emitting devices (e.g., light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), and vertical cavity surface emitting lasers (VCSELs)), and radiation sensing devices (e.g., optical sensors). Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on and/or in a surface of a semiconductor substrate.
Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large, generally cylindrical, silicon single-crystal ingot and subsequently slicing the single-crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is actually used to form active devices on the silicon wafer.
It has been discovered that the speed and power efficiency of semiconductor devices can be improved by electrically insulating the portion of the semiconductor material on a semiconductor substrate that is actually used to form the semiconductor devices from the remaining bulk semiconductor material of the substrate. As a result, so-called “engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively larger host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment. As a result, the base substrate is often referred to in the art as a “handle” or “handling” substrate. The base substrate may also comprise a semiconductor material.
A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), III-V type semiconductor materials, and II-VI type semiconductor materials. For example, an engineered substrate may include an epitaxial layer of III-V type semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (Al2O3) (which may be referred to as “sapphire”). Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V type semiconductor material to form one or more devices on the engineered substrate.
Due to a natural tendency of atoms of different material layers to align with one another when one crystal is formed on another crystal, when a layer of semiconductor material is formed (e.g., epitaxially grown or through layer transfer techniques) over another layer of material (e.g., an underlying layer of dielectric material or an underlying layer of a different semiconductor material), the crystal tends to stretch or “strain” to align with the atoms in the underlying material. The formation and use of strained layers of semiconductor material is difficult because these strained layers develop defects, such as dislocations, due to mismatch of the lattice parameters between adjacent materials. Depending on its particular composition, the layer of semiconductor material may only be grown to a particular thickness, often referred to as a “critical thickness,” before defects and separation of compositional phases begin to develop. The critical thickness of a material is dependent on the lattice structure of the underlying material, the composition of the semiconductor material, and the growth conditions under which the layer of semiconductor material is formed. Dislocations form above a critical thickness when a lattice parameter mismatch exists between the layer of semiconductor material and the underlying substrate material. When forming these layers epitaxially, both a high doping concentration and an increased material thickness are desirable to reduce electrical resistivity. However, as the concentration of dopant and the thickness of the layer of semiconductor material is increased, preserving a crystal structure having low-defect density becomes increasingly difficult.
For example, indium gallium nitride (InXGa1-XN) devices may be formed on an engineered substrate by growing one or more epitaxial device layers each comprising indium gallium nitride (InXGa1-XN) (which together form a “device structure stack”) on a seed layer of gallium nitride formed on the engineered substrate. Any mismatch in the crystal lattices of the adjacent layers of indium gallium nitride may induce strain in the crystal lattice of one or more of the indium gallium nitride device layers, which may effectively limit the thickness of the indium gallium nitride device layer and/or the concentration of indium in the indium gallium nitride device layer. Lattice strain is more problematic in indium gallium nitride device layers having higher indium content and increased thicknesses. The presence of such lattice strain in a layer of semiconductor material may be undesirable for a number of reasons. For example, the presence of lattice strain in a layer of semiconductor material may result in an increased density of defects (e.g., lattice dislocations) in the layer of semiconductor material, undesirable morphology at the surface of the layer of semiconductor material, and may even result in the formation of cracks in the layer of semiconductor material. Furthermore, the presence of lattice strain in a layer of semiconductor material may facilitate the onset of undesirable separation of material phases within the layer of semiconductor material. Unfortunately, currently available substrate materials lattice matched to indium gallium nitride are impractical for high quality materials deposition purposes.
It is difficult to form an indium gallium nitride seed layer on the surface of an engineered substrate in such a manner that the indium gallium nitride seed layer has a lattice parameter that will match that of an indium gallium nitride device layer to be formed thereover. As a result, the crystal lattice of the overlying device layer of indium gallium nitride will be strained upon formation thereof when using the underlying seed layer of indium gallium nitride.
U.S. Pat. No. 7,273,798, issued Sep. 25, 2007 to Lester et al., discloses a gallium nitride device substrate and methods of fabricating the gallium nitride device substrate including a lattice parameter altering element. As disclosed therein, a semiconductor structure may include a substrate, a layer of gallium nitride and a layer containing a lattice parameter altering element. The lattice parameter altering element is disclosed as aluminum or indium. Due to lattice mismatch of the layer of gallium nitride and the layer containing a lattice parameter altering element, the layer containing a lattice parameter altering element is grown in a strained condition so that its lattice parameter conforms to that of the layer of gallium nitride.
Hobart et al., “Compliant Substrates: A Comparative Study of the Relaxation Mechanisms of Strained Films Bonded to High and Low Viscosity Oxides”, J. Elect. Materials, Vol. 29, No. 7, (2000), discloses a method of fabricating a compliant substrate by transferring SiGe islands to a viscous borophosphosilicate glass (BPSG) compliant film. More specifically, a compressively strained heteroepitaxial Si0.7Ge0.3 film bonded to high and low viscosity glass compliant layers were formed by transferring the Si0.7Ge0.3 film to silicon substrates covered with borophosphosilicate glass. At temperatures of near 800° C., relaxation and buckling were observed in the Si0.7Ge0.3 film overlying the borophosphosilicate glass. The Si0.7Ge0.3 film was patterned into small areas to eliminate buckling.
Yin et al., “Strain Relaxation of SiGe Islands on Compliant Oxide,” J. App. Physics, 91(12):9716-9722 (2002), discloses a method of forming an epitaxial Si0.7Ge0.3 film by transferring the epitaxial Si0.7Ge0.3 film to borophosphosilicate glass according to a wafer-bonding technique. After transferring the epitaxial Si0.7Ge0.3 film, the Si0.7Ge0.3 film is patterned into arrays of square islands. The Si0.7Ge0.3 islands on borophosphosilicate glass are annealed resulting in lateral expansion and relaxation. Changing the viscosity of the borophosphosilicate glass did not favor either lateral expansion of the islands or buckling within the islands.
In view of the above, there is a need for methods that can be used to reduce lattice parameter mismatch between adjacent layers, and the resulting lattice strain therein, in semiconductor structures and devices such as, for example, engineered substrates, integrated circuit (IC) devices, radiation emitting devices, and radiation sensor devices.